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Make macros

We can define macros in make - they are typically used to store source file names, object file names, compiler options and library links.

They are simple to define, e.g.:

where (SOURCES: .c = .o) makes .c extensions of SOURCES .o extensions.

To reference or invoke a macro in make do $(macro_name).e.g.:


There are many internal macros (see manual pages) here a few common ones:

- file name part of current dependent (minus .suffix).
- full target name of current target.
- .c file of target.

Appendix contains an example makefile for the WriteMyString modular program discussed in the last Chapter.
Wed Sep 14 10:06:31 BST 1994