We can define macros in make - they are typically used to store source file names, object file names, compiler options and library links.
They are simple to define, e.g.:
where (SOURCES: .c = .o) makes .c extensions of SOURCES .o extensions.
To reference or invoke a macro in make do $(macro_name).e.g.:
There are many internal macros (see manual pages) here a few common ones:
Appendix contains an example makefile for the WriteMyString modular program discussed in the last Chapter.